/*
 *      Simple SPI to Wishbone driver
 *      Copyright (C) 2006 Rick Huang
 *      Revision History:
 *      First release:          Dec 9, 2006
 *
 *    This program is free software; you can redistribute it and/or modify
 *    anyway you wish, as long as this statement is kept intact.
 *     */

#include "spi.h"
#include "gpio.h"
#include "lpc210x_gnuarm.h"

void SPI_Config()
{
	PCB_PINSEL0 &= 0xFFFF00FF;				/* Clear SPI controller pins to 0  */
	PCB_PINSEL0 |= 0x00005500;				/* Enable the SPI controller pins  */
	SPI_SPCCR = 0x08;		                /* SPI clock rate = 0x08           */
	SPI_SPCR = 0x20;                        /* Set SPI mode to master mode     */
}

char SPI_SendByte(char byte)
{
	int timeout = 0;
	SPI_SPDR = byte;
	while ( !(SPI_SPSR & (1 << SPSR_SPIF) ) )
	{
		timeout++;
		if (timeout > SPI_Timeout) break;
	}
	return SPI_SPDR;
}

void SPI_SendStream(char *stream, int length)
{
	int i;
	for (i = 0; i < length; i++)
		SPI_SendByte(stream[i]);
}

/* SPI to Wishbone set the bus address */
void S2W_SetAddress(unsigned addr)
{
	GPIO_OUT_CLR(GPIO_FPGA_CE);
	SPI_SendByte(0x01);	
	SPI_SendByte(addr & 0x00ff);
	SPI_SendByte((addr >> 8) & 0x00ff);
	SPI_SendByte((addr >> 16) & 0x00ff);
	SPI_SendByte((addr >> 24) & 0x00ff);
	GPIO_OUT_SET(GPIO_FPGA_CE);
}

/* SPI to Wishbone read a single byte */
char S2W_ReadByte(unsigned addr)
{
	char a;
	GPIO_OUT_CLR(GPIO_FPGA_CE);
	SPI_SendByte(0x01);	
	SPI_SendByte(addr & 0x00ff);
	SPI_SendByte((addr >> 8) & 0x00ff);
	SPI_SendByte((addr >> 16) & 0x00ff);
	SPI_SendByte((addr >> 24) & 0x00ff);
	GPIO_OUT_SET(GPIO_FPGA_CE);
	GPIO_OUT_CLR(GPIO_FPGA_CE);
	SPI_SendByte(0x04);
	SPI_SendByte(0x00);
	a = SPI_SendByte(0x00);
	GPIO_OUT_SET(GPIO_FPGA_CE);
	return a;
}

/* SPI to Wishbone write a single byte */
void S2W_WriteByte(unsigned addr, char data)
{
	GPIO_OUT_CLR(GPIO_FPGA_CE);
	SPI_SendByte(0x01);	
	SPI_SendByte(addr & 0x00ff);
	SPI_SendByte((addr >> 8) & 0x00ff);
	SPI_SendByte((addr >> 16) & 0x00ff);
	SPI_SendByte((addr >> 24) & 0x00ff);
	SPI_SendByte(data);
	GPIO_OUT_SET(GPIO_FPGA_CE);
}


/* SPI multi byte read function */
void S2W_SetupMultiRead(unsigned addr)
{
	GPIO_OUT_CLR(GPIO_FPGA_CE);
	SPI_SendByte(0x01);	
	SPI_SendByte(addr & 0x00ff);
	SPI_SendByte((addr >> 8) & 0x00ff);
	SPI_SendByte((addr >> 16) & 0x00ff);
	SPI_SendByte((addr >> 24) & 0x00ff);
	GPIO_OUT_SET(GPIO_FPGA_CE);

	GPIO_OUT_CLR(GPIO_FPGA_CE);
	SPI_SendByte(0x05);
	SPI_SendByte(0x00);				// DUMMY data
}

char S2W_MultiRead()
{
	return SPI_SendByte(0x00);
}

void S2W_MultiReadFinish()
{
	GPIO_OUT_SET(GPIO_FPGA_CE);
}

/* SPI multi byte write function */
void S2W_SetupMultiWrite(unsigned addr)
{
	GPIO_OUT_CLR(GPIO_FPGA_CE);
	SPI_SendByte(0x01);	
	SPI_SendByte(addr & 0x00ff);
	SPI_SendByte((addr >> 8) & 0x00ff);
	SPI_SendByte((addr >> 16) & 0x00ff);
	SPI_SendByte((addr >> 24) & 0x00ff);
	GPIO_OUT_SET(GPIO_FPGA_CE);

	GPIO_OUT_CLR(GPIO_FPGA_CE);
	SPI_SendByte(0x03);
}

void S2W_MultiWrite(char data)
{
	SPI_SendByte(data);
}

void S2W_MultiWriteFinish()
{
	GPIO_OUT_SET(GPIO_FPGA_CE);
}