////////////////////////////////////////////////////////////////////////////////
//
// Create Date:    10/05/07
// Module Name:    LED_7seg
// Description:    Convert a 16 bit number into Hex output on the 7seg LED
//                
//
// Revision:
// Revision 0.01 - File Created
//
// File format:		This file has been formated to use tabstop of 4
//
// Development platform: Spartan-3 Nexys from Digilent
//
// Copyright (C) 2007, Rick Huang
//   
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
// 
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// Lesser General Public License for more details.
// 
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
// 
////////////////////////////////////////////////////////////////////////////////

module LED_7seg (mclk, reset, an, ssg, num, pt);

	input mclk;
	input reset;
	output [3:0] an;			// Anode connection
	output [7:0] ssg;			// Cathod connection
	input [15:0] num;			// Number input
	input [3:0] pt;				// Decimal point

	// Divide the incoming clock to a lower frequency
	reg [15:0] clk_divider;
	reg clk_low;
	always @ (posedge mclk)
	begin
		if(reset)
			clk_divider <= 0;
		else begin
			clk_divider <= clk_divider + 1;
			if(clk_divider == 0)
				clk_low <= 1;
			else
				clk_low <= 0;
		end
	end

	// Scan the 7-seg LED
	reg [1:0] digit_scan;
	reg [3:0] an;
	reg [3:0] digit_num;
	reg dec_pt;
	
	// Simple ROM to convert digit to LED segments
	assign ssg[6:0] = (digit_num == 4'h0) ? 7'b1000000 :
					  (digit_num == 4'h1) ? 7'b1111001 :
					  (digit_num == 4'h2) ? 7'b0100100 :
					  (digit_num == 4'h3) ? 7'b0110000 :
					  (digit_num == 4'h4) ? 7'b0011001 :
					  (digit_num == 4'h5) ? 7'b0010010 :
					  (digit_num == 4'h6) ? 7'b0000010 :
					  (digit_num == 4'h7) ? 7'b1111000 :
					  (digit_num == 4'h8) ? 7'b0000000 :
					  (digit_num == 4'h9) ? 7'b0011000 :
					  (digit_num == 4'ha) ? 7'b0001000 :
					  (digit_num == 4'hb) ? 7'b0000011 :
					  (digit_num == 4'hc) ? 7'b1000110 :
					  (digit_num == 4'hd) ? 7'b0100001 :
					  (digit_num == 4'he) ? 7'b0000110 :
					  (digit_num == 4'hf) ? 7'b0001110 : 7'b1111111;
	assign ssg[7] = !dec_pt;
	
	always @ (posedge mclk)
	begin
		if(reset)
			digit_scan <= 0;

		else if(clk_low)
		begin
			digit_scan <= digit_scan + 1;
			case (digit_scan)
				2'b00:
				begin
					an <= 4'b1110;
					digit_num <= num[3:0];
					dec_pt <= pt[0] ? 1 : 0;
				end
				2'b01:
				begin
					an <= 4'b1101;
					digit_num <= num[7:4];
					dec_pt <= pt[1] ? 1 : 0;
				end
				2'b10:
				begin
					an <= 4'b1011;
					digit_num <= num[11:8];
					dec_pt <= pt[2] ? 1 : 0;
				end
				2'b11:
				begin
					an <= 4'b0111;
					digit_num <= num[15:12];
					dec_pt <= pt[3] ? 1 : 0;
				end
			endcase
		end
	end
endmodule