////////////////////////////////////////////////////////////////////////////////
//
// Create Date:    12/09/06
// Design Name:    
// Module Name:    dualmod_div
// Description:    Dual modulus clock divider
//                 
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// File format:		This file has been formated to use tabstop of 4
//
// Development platform: Spartan-3E Starter kit
//
// Copyright (C) 2006, Rick Huang
//   
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
// 
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// Lesser General Public License for more details.
// 
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
// 
// 
////////////////////////////////////////////////////////////////////////////////

module dualmod_div( main_clk, Reset_I, clk_out);

	input main_clk;
	input Reset_I;
	output clk_out;

	// Internal clock net
	// Clock generation, dual mod generator
	parameter Nval = 5'd12;
	parameter Pval = 5'd13;
	parameter Bval = 5'd7;
	parameter Cval = 5'd15;

	reg [4:0] clk_counter;
	reg [4:0] frac_counter;
	wire clk_reset;
	wire NorP;
	reg clk_out;

	always @ (posedge main_clk)
	begin
		if( Reset_I || clk_counter == 0)
		begin
			if(NorP) clk_counter <= Nval;
			else clk_counter <= Pval;
		end else
		begin						// Main counter
			clk_counter <= clk_counter - 1;
		end
	end

	always @ (posedge main_clk)
	begin
		if( Reset_I || frac_counter == 0)
		begin
			frac_counter <= Cval;
		end else
		begin
			if(clk_counter == 0)
			begin
				frac_counter <= frac_counter - 1;
			end
		end
	end

	assign NorP = (frac_counter < Bval) ? 1 : 0;

	always @ (posedge main_clk)  	// Output 1/2 rate divider
	begin
		if( Reset_I )
		begin
			clk_out <= 0;
		end else
		begin
			if(clk_counter == 0)
				clk_out <= ~clk_out;
		end
	end

endmodule