A simple DSP core
This is my simple DSP core. The objective of the project is to create a very simple DSP core that
can utilize the limited multipler resource on a FPGA better.
In most audio filtering design, it is required for the signal to be multiplied and added several
times per sample. However, in a low cost FPGA, there are only 10 to 20 available multiplier
resource available. Thus, it is not possible to implement the entire filter chain using seperate
mutiplier core. Since audio signals are slow, coming in at less than 200k sample/sec, it is
possible to utilize the multiplier resouce better by the mean of time division. The DSP core is
designed to make that task easier.
The core is designed to be simple so it can be modified to each individual project's need. The
key component of the DSP core is the ALU. This DSP core is designed to handle 32 bit fix point
math. All instruction are designed to handle signed number. 16 general purpose registers are
available to be used with 16 reserved register space that can be used for application specific
needs.
The basic instructions are described here:
NOP - No operation
Don't really need to explain this huh?
LDD - Load from data
Load a 32 bit dword from the data memory space
STD - Store to data
Store a 32 bit dword to the data memory space
ADD - Add x to y and store result to z
Simple signed addition
SUB - Substract x from y and store result to z
Simple signed substraction
MUL - Multiply x to y and store the product to z and z+1
Simple signed multiplication. This instruction takes 4 cycle to complete and will use 2 register.
The register used to hold the output must be an even number register.
to store the result in 64 bit format
MULH - Multiply x to y and store the higher 32 bit of the product to z
This instruction is similer to MUL except it only store the higher 32 bit of data.
SHL - Barrel shift to the left
Barrel shifter, up to 15 bits at a time
SHR - Barrel shift to the right
Barrel shifter, up to 15 bits at a time
Version 1 of the core
The is the first version of the DSP core, more or less a proof of concept core. Each instruction
takes 3 cycles to complete with the exception of the MUL instruction, which takes 4 cycles to
complete. The core is expected to run at 75MHz, resulting about 25M calculation/sec.
Version 1 of the assembler
A quick and dirty compiler that generate the binary code for the DSP core.
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Page last updated: Feb 22nd, 2009
Email: rihuang ([at]) gmail (*dot*) com
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